80 #define SLAVE_ADDRESS 0x48
86 WDT_A_hold(WDT_A_BASE);
93 GPIO_setAsPeripheralModuleFunctionInputPin(
95 GPIO_PIN2 + GPIO_PIN3,
96 GPIO_PRIMARY_MODULE_FUNCTION
105 EUSCI_B_I2C_initSlaveParam
param = {0};
106 param.slaveAddress = 0x48;
107 param.slaveAddressOffset = EUSCI_B_I2C_OWN_ADDRESS_OFFSET0;
108 param.slaveOwnAddressEnable = EUSCI_B_I2C_OWN_ADDRESS_ENABLE;
109 EUSCI_B_I2C_initSlave(EUSCI_B0_BASE, &
param);
111 EUSCI_B_I2C_enable(EUSCI_B0_BASE);
113 EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,
114 EUSCI_B_I2C_TRANSMIT_INTERRUPT0 +
115 EUSCI_B_I2C_STOP_INTERRUPT
118 EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,
119 EUSCI_B_I2C_TRANSMIT_INTERRUPT0 +
120 EUSCI_B_I2C_STOP_INTERRUPT
124 __bis_SR_register(CPUOFF + GIE);
128 #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
129 #pragma vector=USCI_B0_VECTOR
131 #elif defined(__GNUC__)
132 __attribute__((interrupt(USCI_B0_VECTOR)))
136 switch(__even_in_range(UCB0IV, USCI_I2C_UCBIT9IFG))
140 case USCI_I2C_UCALIFG:
142 case USCI_I2C_UCNACKIFG:
144 case USCI_I2C_UCSTTIFG:
146 case USCI_I2C_UCSTPIFG:
149 case USCI_I2C_UCRXIFG3:
151 case USCI_I2C_UCTXIFG3:
153 case USCI_I2C_UCRXIFG2:
155 case USCI_I2C_UCTXIFG2:
157 case USCI_I2C_UCRXIFG1:
159 case USCI_I2C_UCTXIFG1:
161 case USCI_I2C_UCRXIFG0:
163 case USCI_I2C_UCTXIFG0:
164 EUSCI_B_I2C_slavePutData(EUSCI_B0_BASE,
167 case USCI_I2C_UCBCNTIFG:
168 GPIO_toggleOutputOnPin(
173 case USCI_I2C_UCCLTOIFG:
175 case USCI_I2C_UCBIT9IFG:
MPU_initThreeSegmentsParam param